1. Technical Field
The present application relates to semiconductor memory devices, including systems and methods for controlling voltage levels associated with output operations of semiconductor memory devices.
2. Related Art
Semiconductor memory devices are known that are capable of storing bits of data in a memory array. For example, NAND flash memories include an array of memory cells for storing data. FIG. 1A shows a block diagram of some basic components of a typical NAND flash memory device 100. The memory device 100 includes a memory array 102, which includes some number “i” of memory strings MS1-MSi. Each of the memory strings MS1-MSi includes a respective group of “j” memory cells that are connected in series between a common source line and a respective one of bit lines BL1-BLi. Thus, the memory array 102 includes an i by j array of memory cells, where i and j are integers that can vary depending on the capacity of the memory array 102.
Each of the memory strings MS1-MSi includes an equal number j of series-connected floating gate transistors (not shown), each of which constitutes a respective memory cell. The gate of each of the floating gate transistors is controlled by a respective one of the word lines WL1-WLj according to signals from a row decoder 104. The word lines WL1-WLj connect to all of the memory strings MS1-MSi; each of the word lines WL1-WLj controls the gate of a respective floating gate transistor in each of the memory strings MS1-MSi.
A string select line SSL and a ground select line GSL also connect to all of the memory strings MS1-MSi. Each of the memory strings MS1-MSi includes a respective string select transistor (not shown) and a respective ground select transistor (not shown). The string select line SSL controls the string select transistors of the memory strings MS1-MSi; the ground select line GSL controls the ground select transistors of the memory strings MS1-MSi. The string select transistors control the connections between the memory strings MS1-MSi and their respective bit line BL1-BLi; the ground select transistors control the connections between the memory strings MS1-MSi and the common source line.
The voltage level of the source line is controlled by a source line control circuit 106. The respective voltage levels of the bit lines BL1-BLi are controlled by respective sense amplifiers 108a-108i and clamp transistors CT1-CTi. The applied voltage levels can vary depending on the type of operation that is being performed on the memory cells. Examples of typical operations include read and write operations, where the write operations can differ depending on whether a memory cell is being programmed or erased.
It takes some amount of time to bring the various control lines to the respective voltage levels needed to perform the various operations involving memory cells of the memory array 102. So, some devices are configured to maintain some minimum voltage level, for example on the bit lines BL1-BLi, so that the amount of time needed to perform various operations can be reduced. However, for many electronic devices, power consumption is an important issue. Maintaining such minimum voltage levels may serve to speed up memory processes, but it suffers the disadvantage of consuming additional electrical power. So, for example, in devices that primarily rely upon battery power, this increase in power consumption may advantageously provide for faster memory, but it does so at the cost of reduced battery life.
Such issues are well-known, and have resulted in a variety of schemes involving “standby” modes while still periodically pre-charging various control lines. For example, in the memory device 100 shown in FIG. 1, a bit line driver 110 can provide a bit-line clamp signal BLCLAMP to the clamp transistors CT1-CTi in order to allow voltages from the respective sense amplifiers 108a-108i to pre-charge bit lines BL1-BLi in anticipation of an upcoming read operation. The sense amplifiers 108a-108i are provided with a supply voltage VDD, which is selectively applied to the respective bit lines BL1-BLi depending upon the condition of the respective clamp transistors CT1-CTi.
Referring to FIG. 1B, before a bit line BL is pre-charged, the sense-amplifier side of the clamp transistor CT (i.e., the drain) is at a voltage level equivalent to VDD, while the gate is at 0 volts and the bit-line side (i.e., the source) is at 0 volts or floating. As shown in FIG. 1C, it is well known that MOSFET transistors include a number of intrinsic coupling capacitances, including a gate to source capacitance represented in FIG. 1C as capacitor CGS. The bit-line clamp signal BLCLAMP and resulting bit line voltage are shown in FIG. 1D. These signals have a very steep transition, allowing for quickly pre-charging the bit line. However, the gate to source capacitance CGS causes some amount of reverse coupling of the bit-line clamp signal BLCLAMP. As a result, the actual BLCLAMP voltage will increase from an expected voltage level (shown by the solid line) to a higher actual level (shown by the broken line). As a result, the bit-line clamp signal BLCLAMP strays higher than the design target level. Also, as shown in FIG. 1D, the bit line pre-charge voltage level will likewise stray higher than the design target level. Thus, the coupling capacitance of the MOSFET can cause incorrect voltage levels to occur within the memory device, which in turn can lead to errors during memory operations.
Also, depending on the operation being performed, the voltage levels of neighboring bit lines BL1-BLi may differ. For example, during a read operation, one bit line may be raised to 0.7 volts, while a neighboring bit line is at ground (0 volts). As semiconductor devices have been reduced in scale, the distance between neighboring bit lines has been reduced as well. As a result, the voltage differences between neighboring lines, such as neighboring bit lines, can result in a coupling effect, which basically means that the voltage on one bit line can influence the voltage level of another bit line. The coupling effect is an undesirable aspect of memory devices, because it can cause errors in read and write operations of the memory.
As a result, it is desirable to find ways of reducing and eliminating unwanted effects due to capacitive coupling within the MOSFET, as well as elsewhere such as between neighboring control lines.